The density of devices fabricated on semiconductor substrates continues to increase due in large part to decreasing feature sizes. For example, today's ultra large scale integrated (ULSI) devices, such as 16 megabit (Mb) dynamic random access memories (DRAMs) (illustrated in U.S. Pat. No. 5,202,279) issued to Chung et al.) are built using 0.5 micron technology while tomorrow's 64 MB DRAM are projected to incorporate 0.35 micron features. In order for minimization to continue, the processing used to manufacture and ensure the reliability of such sub-micron devices must continually be challenged, developed, and refined.
One important semiconductor processing area in need of improvement is metallization. Chapter 9, on pages 375-421, of VLSI Technology Second Edition, 1988, by S. M. Sze of AT&T Bell Laboratories discusses metallization as does Chapter 10, on pages 518-578, of Semiconductor Integrated Circuit Processing Technology, 1990, by W. R. Runyan and K. E. Bean of Texas Instruments.
Metallization provides interconnection between contacts on devices and between devices and the outside world. To make electrical connection between devices and the outside world, multilevels of metal are used. Typically, a recess (hole or via) is bored through a dielectric covering a first level of metal. The hole is filled with conductive material and a second level of metal is applied. The conductive material in the via provides electrical connection between the first and the second levels of metal.
As device feature sizes shrink, the aspect ratio of the vias increase. The aspect ratio is obtained by dividing the depth of the via by the width (diameter) of the via. Ultra Large Scale Integrated (ULSI) circuit devices such as the above described 16MB DRAM have vias around 1.5 microns deep and around 0.6 microns wide, thus giving them high aspect ratios on the order of about 2.5.
In ULSI multilevel metallization systems, interconnect via reliability performance problems can be associated with many process/design related factors. In particular, increasing via aspect ratios tend to emphasize via etch and clean up related issues. Etch residues produced by the highly-passivating etch chemistries such as CHF.sub.3, CF.sub.4, and C.sub.2 F.sub.6 are becoming harder to remove completely, and more aggressive solvents have to be used. In the case of aluminum leads, this puts the exposed aluminum lead surfaces to a greater risk of damage. Tighter design rules require the use of highly directional and energetic reactive ion etch plasmas which then also expose the underlying aluminum to erosion or trenching by lack of selectivity. A trend towards all dry post via etch cleanup processes aids to prevent solvent induced defects but may create further damage to the aluminum surface by oxidation, whereas attempts to sinter the newly-etched via holes to burn off organic residues put the aluminum at risk of hillocking into the vias.
Electromigration undesirably affects via interconnect performance. Electromigration induced failure is probably the most important mode of failure in aluminum lines. Prior attempts to improve electromigration performance have involved utilizing antireflection coating (ARCs) capping layers. These ARCs are typically thin layers of various refractory metals such as TiN and TiW. The capping layers have been put above and below the aluminum leads to improve electromigration characteristics as discussed in the following papers: "A Highly Reliable Aluminum Metallization For Micron and Submicron VLSI Applications" by Shen et al., June 1986 V-MIC Conference; "Electromigration Improvements with Titanium Underlay and Overlay in Al(Cu) Metallurgy" by Estabil et al., June 1991 VMIC Conference; and, "Texture Effects On The Electromigration Behavior of Layered Ti/A1Cu/Ti Films" by Rodbell et al. 1992 Materials Research Society Symposium Volume 265.
Despite providing improvements in electromigration, these thin capping layers still do not adequately protect the portion of the aluminum leads lying underneath high aspect ratio vias. The etch chemistries are typically not selective to the antireflective coatings and since these coatings are very thin, it is possible to etch into the underlying aluminum when etching the vias. This provides undesirable higher via resistance and greater standard deviation across a semiconductor wafer surface. Etching into the aluminum during the via etch exposes the aluminum to contamination from the etching plasma, the ambient, the cleaning agents necessary to remove etch residues, etc.
It is accordingly an object of the invention to improve the manufacturability and reliability of vias.
It is an additional object of the invention to provide an improved metal junction for interconnects in semiconductor devices.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification and drawings.